In recent years, there has been a growing need for further reducing the size and weight of portable electronic devices mounted with, for example, a liquid crystal display device or an organic electroluminescent display device (OEC display), such as cellular phones and PDAs. A trend, therefore, has been toward reducing the size of regions around display regions, that is, narrow frames, and studies have been intensively carried out to achieve it. Another trend has focused attention on display devices having a full-monolithic display device substrate, which can be designed to be thinner and produced at low cost, and these display devices having a full-monolithic display device substrate have been increasingly produced. The full-monolithic display device substrates are substrates having a peripheral circuit integrally formed thereon for driving a driver circuit or the like.
FIG. 7 are cross-sectional views schematically illustrating a frame region of a conventional liquid crystal display device. FIG. 7 (a) illustrates a terminal area, and FIG. 7 (b) illustrates a peripheral circuit region. In the terminal area of the conventional liquid crystal display device 600, as shown in FIG. 7 (a), a TFT substrate 111, which is a display device substrate, and an FPC board 170 are connected through an ACF 180.
In the terminal area, as shown in FIG. 7 (a), The TFT substrate 111 includes an insulating substrate 121, a base coat film 122, a gate insulating film 124, gate electrodes 125, an inorganic insulating film 141 serving as an interlayer insulating film, a connection terminal (external connection terminal) 126 in a first wiring layer 161, and an organic insulating film 151a serving as a protective film, and these components are stacked in this order from the insulating substrate 121. A pad 127 is provided on an end portion of the connection terminal 126.
In the peripheral circuit region, as shown in FIG. 7 (b), the TFT substrate 111 includes the insulating substrate 121, the base coat film 122, a semiconductor layer 123, the gate insulating film 124, the gate electrode 125, the inorganic insulating film 141 serving as an interlayer insulating film, source/drain electrodes 128 and extending lines 130a in the first wiring layer 161, the organic insulating film 151a serving as an interlayer insulating film, extending lines 130b in a second wiring layer 162, and an organic insulating film 151 serving as a protective film, and these components are stacked in this order from the insulating substrate 121.
A structure in which a well-planarized organic insulating film like the organic insulating film 151a is formed as a planarizing film has been proposed as a technique to reduce irregularity caused by layers at lower levels than the organic insulating film, such as the first wiring layer 161 and the TFT 129, and to prevent short circuits of lines at upper levels than the organic insulating film, such as the lines in the second wiring layer 162, even if the lines are extended.
For example, Patent Document 1 discloses a display device in which an aluminum film used for a wiring in the inside of a panel (i.e. in a pixel region or a display region) is connected in the inside of the panel to a metal film at a lower level than the aluminum film and the metal film is extended outward from the panel with the metal film.
Patent Document 2 discloses a technique for semiconductor devices, which is a method for forming a multilayer wiring structure including: forming through holes in an insulating film; covering the through holes with an organic film before removal of a resist; performing an O2 plasma treatment; and performing a treatment with a resist removing solution to remove the organic film covering the through holes as well as the resist. This technique was established to reduce damage to the wall surfaces of the through holes in the interlayer insulating film in the O2 plasma treatment and therefore to avoid an increase in hygroscopicity caused by such damage. This technique also aims to prevent faulty contact between first lines at a lower level than the interlayer insulating film and second lines at an upper level than the interlayer insulating film, and to reduce electromigration of the second lines caused by surface irregularity.    [Patent Document 1]
Japanese Kokai Publication No. Hei-3-58019    [Patent Document 2]
Japanese Kokai Publication No. Hei-3-183756